1. Field of the Invention
The present invention relates to an integrated circuit testing device for testing digital integrated circuits, and, in particular, to an integrated circuit testing device with improved testing capabilities.
2. Description of the Prior Art
An example of an integrated circuit testing device which tests the operation of a digital circuit as a DUT (Device Under Test) is an unit with the configuration shown in FIG.1.
The integrated circuit testing device shown in FIG.1 comprises a waveform formatter 1 as a small test signal generation means and a power amplification circuit 2.
The waveform formatter 1 inputs an input test pattern represented as logic "1" or logic "0", and timing data which shows the timing of the changes between high level power and low level power of a test signal which is provided to a DUT 3.
The waveform of the input test pattern is then shaped into a small test signal at low power corresponding to a test signal using the timing data. The waveform-shaped small test signal is provided from the waveform formatter 1 to a driver 4, which is an element of the power amplifier circuit 2.
The power amplifier circuit 2 comprises the driver 4, a high power source 5 for high level signal amplification, and a low power source 6 used for low level signal amplification. The power amplifier circuit 2 amplifies the power of the small test signal produced in the waveform formatter 1. Specifically, in the case of a small test signal 20 at high level, the power set by a high level setting signal 22 which sets the high level side of a test signal 21 is supplied to the driver 4 from the high power source 5 for high level signal amplification. In addition, in the case of a small test signal 20 at low level, the power set by a low level setting signal 23 which sets the low level side of a test signal 21 is supplied to the driver 4 from the low power source 6 for low level signal amplification. This power is used to amplify the power of the small, low-powered test signal 20 to provide a test signal with a set level. The power-amplified test signal is supplied from the driver 4 to an input pin of the DUT 3. Based on this test signal, the test results of the DUT 3 which is being operated are provided to a comparator (not shown) or the like and the action of the DUT 3 is judged as good or unsatisfactory.
In this manner, the test signal 21 supplied to a DUT from a conventional integrated circuit testing device is stipulated only by the timing data and the high level and low level setting signals 22, 23.
However, when a CMOS circuit is tested, the rise and fall of the input signal are at a medium potential so that a window-type current or a through-type current flows in the circuit.
Accordingly, in order to evaluate and test a condition of this type consideration must be given to the rise and fall times of the test signal 21.
Also, because the more recent integrated circuits operate at high speeds, the rise and fall times of the signals input to these integrated circuits have become shorter. Accordingly, to correctly evaluate and test these integrated circuits, it is absolutely necessary to include the rise and fall times in the items which are measured.
However, in a conventional integrated circuit testing device, as outlined above, the rise and fall times of the test signals cannot be varied.
Accordingly, it is not possible to take the rise and fall times of the test signal 21 of the DUT 3 into account when evaluating the integrated circuit. This is a problem.